Many electronic devices and systems (e.g., computers, tablets, digital televisions, and cellular phones) control their internal operations based on timing of a clock signal or multiple clock signals. Such devices and systems usually have a PLL to generate the clock signal based on a reference clock signal. For timing accuracy, the PLL performs a phase alignment operation in order to align the phase (e.g., an edge) of the generated clock signal with the phase (e.g., an edge) of the reference clock signal. The phase alignment operation is part of an overall locking operation of the PLL. The PLL can be in a locked state after the generated clock signal is aligned with the reference clock signal. In some conventional PLLs, such as some digital PLLs and low band-width PLLs, the phase alignment operation can be a lengthy process and can become a bottleneck for the overall locking operation of such conventional PLLs.